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NXP Semiconductors /LPC176x5x /SYSCON /PLL1CFG

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Interpret as PLL1CFG

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0MSEL10PSEL1 0RESERVED

Description

PLL1 Configuration Register

Fields

MSEL1

PLL1 Multiplier value. Supplies the value M in the PLL1 frequency calculations.
PSEL1

PLL1 Divider value. Supplies the value P in the PLL1 frequency calculations.
RESERVED

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data